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Semiconductor
August 1997
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HI20206
Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter
Features
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit * Maximum Conversion Speed . . . . . . . . . . . . . . . 35MHz * RGB 3-Channel Input/Output * Differential Linearity Error . . . . . . . . . . . . . . . 1/2 LSB * Digital Input Voltage . . . . . . . . . . . . . . . . . . . .TTL Level * Output Voltage Full-Scale . . . . . . . . . . . . . . 1VP-P (Typ) * Low Power Consumption . . . . . . . . . . . . . 360mW (Typ) * +5V Single Power Supply * Direct Replacement for Sony CX20206
Description
The HI20206 is a triple 8-bit, high-speed, bipolar D/A converter designed for video band use. It has three separate, 8-bit pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. For lower CMOS power consumption, refer to the HI1178.
Ordering Information
PART NUMBER HI20206JCP TEMP. RANGE (oC) -20 to 75 PACKAGE 42 Ld PDIP PKG. NO. E42.6B-S
Applications
* Digital TV * Graphics Display * High Resolution Color Graphics * Video Reconstruction * Instrumentation * Image Processing * I/Q Modulation
Pinout
HI20206 (PDIP) TOP VIEW
R5 R6 R7 R8 G1 G2 G3 G4 G5 G6 G7 G8 B1 B2 B3 B4 B5 B6 B7 B8 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 R4 41 R3 40 R2 39 R1 38 NC 37 DGND 36 NC 35 ROUT 34 NC 33 GOUT 32 NC 31 BOUT 30 NC 29 AVCC 28 NC 27 VSET 26 VREF 25 AGND 24 NC 23 NC 22 DVCC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
4111.1
10-1
HI20206 Functional Block Diagram
DGND 37
R1 R2 R3 R4 R5 R6 R7 R8 G1 G2 G3 G4 G5 G6 G7 G8 B1 B2 B3 B4 B5 B6 B7 B8
39 40 41 42 1 2 3 R 4 5 6 7 8 9 10 11 R 12 13 14 15 16 17 18 19 R 20 R 2R INPUT BUFFER (B) 2 DECODER 3 CURRENT SWITCH (B) 3 R R R R R R 2R INPUT BUFFER (G) 6 2 DECODER 3 CLOCK SYNCHRONIZING CIRCUIT 2R R INPUT BUFFER (R) CURRENT SWITCH (R) 2 DECODER 3 3 R R R R R R 2R 2R 2R 2R
33 ROUT
6
6
33 GOUT 3 R R 6 CURRENT SWITCH (G) R R R R 2R 2R 2R 2R
31 BOUT R 2R 2R 2R 2R
6
6
29 AVCC CLOCK BUFFER INTERNAL REFERENCE VOLTAGE SOURCE 27 VREF
21 CLK 22 DVCC 23 AGND
+ 26 VRET
10-2
HI20206 Pin Descriptions
PIN NO. 1 To 20 39 To 42 SYMBOL R1 To R8 G1 To G8 B1 To B8 EQUIVALENT CIRCUIT
DVCC 22
DESCRIPTION Digital Input pin. From pins 39 to 42 and from 1 to 4 are for RED. R1 is MSB and R8 is LSB. From pins 5 to 12 are for GREEN. G1 is MSB and G8 is LSB. From pins 13 to 20 are for BLUE. B1 is MSB and B8 is LSB.
39 - 42 1 ~ 20
37 DGND
21
CLK
DVCC 22
Clock Input pin.
21
37 DGND
22 23 24 25 26
DVCC NC AGND VSET
AVCC 29 54K
Digital VCC . No Connect. Analog GND. Bias Input pin. Normally, apply 0.8V.
26
25 AGND
27
VREF
AVCC 29
Internal Reference Voltage Output pin 1.2V (Typ). A pulldown resistance is necessary externally.
27 20P
25 AGND
10-3
HI20206 Pin Descriptions
PIN NO. 28 29 30 31 (Continued) EQUIVALENT CIRCUIT No Connect. Analog VCC . Vacant pin but connect to AVCC (Note 1).
AVCC 29 RO 31
SYMBOL NC AVCC NC BOUT
DESCRIPTION
Analog Output pin for BLUE.
25 AGND
32 33
NC GOUT
AVCC 29 RO 33
Vacant pin but connect to AVCC (Note 1). Analog Output pin for GREEN.
25 AGND
34 35
NC ROUT
AVCC 29 RO 35
Vacant pin but connect to AVCC (Note 1). Analog Output pin for RED.
25 AGND
36 37 38 NOTE:
NC DGND NC
Vacant pin but connect to AVCC (Note 1). Digital GND. No Connect.
1. Pins 30, 32, 34 and 36 are vacant, but in order to reduce interference between the individual RGB outputs, connect them to AVCC .
10-4
HI20206
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 7V Input Voltage (Digital) (VI , VCLK) . . . . . . . . . . . . . . . . . -0.3V to VCC Output Voltage (Analog) (VSET) . . . . . . . . . . . . . . VCC -2.1V to VCC Output Current Analog (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 10mA VREF Pin (IREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Supply Voltage Range (Typ) . . . . . . . . . . . . . . . . . . . . . . . 5V to 10V
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Recommended Operating Conditions
Supply Voltage AVCC , DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V AVCC-DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 0.2V AGND-DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Digital Input Voltage H Level (VIH , VCLKH) . . . . . . . . . . . . . . . . . . . . . . . .2.0V to DVCC L Level (VIL , VCLKL) . . . . . . . . . . . . . . . . . . . . . . . . DGND to 0.8V VSET Input Voltage (VSET). . . . . . . . . . . . . . . . . . . . . . .0.7V to 0.9V VREF Pin Current (IREF). . . . . . . . . . . . . . . . . . . . . . -3mA to -0.4mA Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ns Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Monotonic Differential Linearity Error Integral Linearity Error Maximum Conversion Speed Full Scale Output Voltage (Note 3)
TA = 25oC, AVCC = DVCC = 5V, AGND = DGND = 0V SYMBOL RSL MNT DLE ILE fMAX VOFS FSR VOFFSET RO ID VSET - AGND = 0.8V, RL > 10k, IREF = -400A VI = DVCC VI = DGND VCLK = DVCC VCLK = DGND VSET - AGND = 0.8V IREF = -400A VSET - AGND = 0.8V, RL > 10k VSET - AGND = 0.8V, RL > 10k, CL < 20pF TEST CONDITIONS MIN -0.5 -0.4 35 0.85 0 -40 270 54 -10 -10 -10 -5 1.08 12 3 D/A OUT: 1VP-P , RL>10k, CL<20pF, fDATA = 7MHz, fCLK = 14MHz, See Figure 5 TYP 8 Guarantee 1.0 4 -6 340 72 1.2 0.6 0 0 3 0 -0.3 1.20 -40 MAX 0.5 0.4 1.15 8 0 420 90 20 10 10 10 30 10 0 1.32 -33 UNITS Bit LSB % of Full Scale MHz VP-P % mV mA A A A A A A A V ns ns dB
RGB Output Voltage Full Scale Ratio (Note 4) Output Zero Offset Voltage Output Resistance Dissipation Current Digital Data Input Current H Level L Level Clock Input Current VSET Input Current Internal Reference Voltage Set-Up Time Hold Time Crosstalk Among R, G and B Upper 2 Bits Lower 6 Bits Upper 2 Bits Lower 6 Bits H Level L Level
IIH(U) IIH(L) IIL(U) IIL(U) ICLKH ICLKL ISET VREF tS tH CT
10-5
HI20206
Electrical Specifications
PARAMETER Glitch Energy TA = 25oC, AVCC = DVCC = 5V, AGND = DGND = 0V (Continued) SYMBOL GE TEST CONDITIONS VSET - AGND = 0.8V, RL>10k, fCLK = 1MHz, Digital Ramp Output, See Figure 6 (Note 5) VSET - AGND = 0.8V See Figure 4 MIN TYP 160 MAX UNITS pV/s
Rise Time (Note 6) Fall Time (Note 6) Settling Time NOTES: 3. AVCC - VO . 4. Maximum value among
tr tf tSET
-
5.5 5.0 16
-
ns ns ns
VO FS ( R ) VO FS ( G ) VO FS ( B ) 100 x ----------------------- - 1 , 100 x ----------------------- - 1 , or 100 x ----------------------- - 1 . VO FS ( G ) VO FS ( B ) VO FS ( R )
5. Observe the glitch which is generated when the digital input varies as follows: 0 0 1 1 1 1 1 1 --0 1 0 0 0 0 0 0 01 1 1 1 1 1 1 1 -- 1 0 0 0 0 0 0 0 10 1 1 1 1 1 1 1 -- 1 1 0 0 0 0 0 0 6. The time required for the D/A OUT to arrive at 90% of its final value from 10%. INPUT CORRESPONDING TABLE INPUT CODE MSB 11111111 * * * 10000000 * * * 00000000 VCC + VOFFSET -0.5V * * * VCC + VOFFSET -1.0V LSB VCC + VOFFSET OUTPUT VOLTAGE
NOTE: In case the output voltage full scale is 1V (1 LSB = 3.92mV).
Test Circuits
37 39 - 42 1~4 35 5 ~ 12 8 (G) D1 ~ D8 D8 8 (B) DGND 25 33F CLK TTL LEVEL CLK HI20206 21 22 13 ~ 20 GOUT 33 31 29 27 26 BOUT AVCC VREF VSET + 3K V V ROUT
DVCC D1 D2
D1 ~ D8 8 (R) D1 ~ D8
-
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUITS
10-6
HI20206 Test Circuits
(Continued)
(MSB) OUT D1 D2 8-BIT COUNTER (TTL OUTPUT) (LSB) D8
D1 ~ D8 8 (R) D1 ~ D8
37 39 - 42 1~4 35 5 ~ 12 GOUT 33 31 13 ~ 20 29 26 25 32F 21 22 HI20206 VSET + BOUT ROUT
DIGITAL RAMP WAVEFORM GENERATION
8 (G) D1 ~ D8 8 (B)
OSCILLOSCOPE RIN = 1M CIN = 10pF BW = 20MHZ
IN
12.5K V
-
CLK MCLK f = 35MHz TTL LEVEL RECTANGULAR WAVE CLK
AGND
DGND
2ns ~ 10ns D1 ~ D8 AVCC DVCC
TIMING BETWEEN CLK AND DATA
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
D1 ~ D8 DVCC 8 (R)
37 39 - 42 1~4 35 5 ~ 12 GOUT 33 BOUT 31 13 ~ 20 29 27 26 25 AVCC VREF VSET + 3K V 33F V ROUT
8 (G)
8 (B)
-
CLK TTL LEVEL CLK
21 HI20206
22
FIGURE 3. OUTPUT VOLTAGE FULL SCALE PRECISION, RGB OUTPUT VOLTAGE FULL SCALE RATIO, AND OUTPUT ZERO OFFSET VOLTAGE TEST CIRCUITS
10-7
HI20206 Test Circuits
(Continued)
HI20206 37 D1 ~ D8 OBSERVE DATA WAVEFORM WITH AN OSCILLOSCOPE RIN = 1M BW = 200MHz 8 (R) 39 - 42 1~4 35 330 51 5 ~ 12 8 (G) 13 ~ 20 8 (B) 31 330 51 50 47 29 26 CLK 21 (TTL)
1/
1m COAXAL CABLE ROUT COAXAL CABLE 50 GOUT OBSERVE WITH AN OSCILLOSCOPE
33 330 51
COAXAL CABLE
50 BOUT
COAXAL CABLE (1m)
1.2K
COAXAL CABLE
50
VSET +
12.5K
25 22
-
33F
2
DIVIDER f = 35MHz TTL LEVEL
1.2K COAXIAL CABLE (1m)
47 PULSE GENERATOR 8082A (YHP)
50
OBSERVE CLK WITH AN OSCILLOSCOPE RIN = 1M BW = 200MHz
f = 35MHz TTL LEVEL RECTANGULAR WAVE AGND D DELAY ADJUSTMENT PULSE GENERATOR 8082A (YHP) DGND AVCC DVCC
FIGURE 4. SET-UP TIME, HOLD TIME, AND RISE AND FALL TIME TEST CIRCUITS
D1 ~ D8 8 (R)
39 - 42 1~4
37 ROUT 50 EXIT FET PROBE P6202 (TEKTRONIX) AVCC VSET + 12.5K SPECTRUM ANALYZER
5 ~ 12 8 (G) f = 7MHz TTL LEVEL RECTANGULAR WAVE
1/
35 GOUT 33
13 ~ 20 8 (B)
2
BOUT 31
DIVIDER
30, 32 34, 36 29 26
-
MCLK f = 14MHz TTL LEVEL RECTANGULAR WAVE
25 33F 21 CLK HI20206 22
Measuring Method, in case the measuring crosstalk of G R: 1. Apply the data to G only, and measure the power of the frequency component of the data at ROUT . 2. Apply the data to R only, and measure the power of the frequency component of the data at ROUT . 3. Take the difference of the above two powers; the unit is in dB. FIGURE 5. CROSSTALK AMONG R, G, AND B TEST CIRCUIT
10-8
(
(
(
(
(
(
RIN = 1M BW = 200MHz
HI20206 Test Circuits
(Continued)
(MSB) D1 D2 8-BIT COUNTER (TTL OUTPUT)
OUT
D1 ~ D8 8 (R) D1 ~ D8
37 39 - 42 1~4 35 5 ~ 12 GOUT 33 31 13 ~ 20 29 27 26 25 33F 21 22 HI20206 VREF VSET BOUT ROUT
DIGITAL RAMP WAVEFORM GENERATION
(LSB) D8 100pF
8 (G) D1 ~ D8 8 (B)
IN
OSCILLOSCOPE RIN = 1M CIN = 20PF BW = 5MHZ 3K V
+
-
CLK MCLK f = 35MHz TTL LEVEL RECTANGULAR WAVE
AGND CLK 5ns ~ 300ns D1 ~ D8
DGND
AVCC
DVCC
TIMING OF CLK AND DATA
FIGURE 6. GLITCH ENERGY TEST CIRCUIT
37 DATA (R) (TTL LEVEL) (G) 8 39 - 42 1~4 35 8 5 ~ 12 GOUT 33 (B) 8 BOUT 31 30, 32 34, 36 29 27 26 + VREF VSET 3K AGND DGND AVCC DVCC 13 ~ 20 ROUT
-
R LPF R LPF R LPF BW = 16MHz BOUT GOUT ROUT
+
-
+
-
+
-
25 CLK (TTL LEVEL) 33F CLK 21 HI20206 22
R is matching resistance for LPF.
FIGURE 7. APPLIED CIRCUIT EXAMPLE
10-9
HI20206 Timing Diagram
t1 tPW1 t12 t2 tPW0 t3 t34 t4
CLK tX tY
VTH = 1.5V
DATA VTH = 1.4V tH tH 100% 0% 90% 10%
tS
tS VTH: THRESHOLD LEVEL
D/A OUT 10% 0% 100% 90%
tr
tf
NOTE: At the time t = tX , the data of individual bits are switched and thereafter, when the CLK becomes L H at t = t2 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. [In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = t12)].
NOTE: At the time t = tY , the data of individual bits are switched and thereafter when the CLK becomes L H at t = t4 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. [In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = t4)].
FIGURE 8. TIMING CHART
Notes On Use
(1) Setting of pin 26 (VSET) The full scale of the D/A output voltage changes by applying voltage to pin 26 (VSET). When load is connected to pin 27 (VREF), DC voltage of 1.2V is issued and the said voltage is dropped to 0.8V by resistance division. When the 0.8V is applied to pin 26 (VSET), the D/A output of 1VP-P can be obtained. (Example of use):
RESISTANCE R (k)
See R vs IREF of Figure 14. The calculation expression is as follows: R = VREF /IREF . 2. Adjust the volume so that the RGB output voltage full scale becomes 1V. (At this point, it becomes R1: R2 = 1:2).
5.0
27 26 25
VREF R1 VSET R2
1.0
R
0.3 AGND
FIGURE 9.
(Adjustment Method) 1. The resistance R is determined in accordance with the recommended operating condition of IREF , (current flowing through resistance R).
0.1 0.1
0.2
1 PIN CURRENT IREF (mA)
5
FIGURE 10. RESISTANCE vs VREF PIN CURRENT
10-10
HI20206
(2) Phase Relationship Between Data and Clock In order to obtain the desired characteristics as a D/A converter, it is necessary to set the phase relationship correctly between the externally applied data and clock. Satisfy the standard of the set-up time (tS) and hold time (tH) indicated in the electrical characteristics. As to the meaning of tS and tH , see the timing chart. Moreover, the clock pulse width is desired to be as indicated in the recommended operating condition. (3) Regarding the Load of D/A Output Pin Receive the D/A output of the next stage with high impedance. In other words perform so that it becomes as follows: RL > 10k CL < 20pF. The temperature characteristics indicated in the characteristics diagram has been measured under this condition. However, when it is made RL 10k the temperature characteristics may change considerably. In addition, when it is made to CL 20pF, the rise and fall of the D/A output become slow and will not operate at high speed. (4) Noise Reduction Measures As the D/A output voltage is a minute voltage of approximately 4mV per one step, ingenuity is required in reducing the noise entering from the outside of the IC as much as possible. Therefore, use the items given below as reference. * When mounting onto the printed board, allow as much space as possible to the ground surface and the VCC surface on the board and reduce the parasitic inductance and resistance. * It is desirable that the AGND and DGND be separated in the pattern on the board. It is similar with AVCC and DVCC . As shown in the diagram below, for example, it is recommended that the wiring to the electric supply of AGND and DGND as also AVCC and DVCC be conducted separately, and then making AGND and DGND as also AVCC and DVCC in common right near the power supply respectively. * Insert in parallel a 47F tantalum capacitor and a 100pF ceramic capacitor between the VCC surface on the printed board and the nearmost ground surface. (A of diagram below). It is also desirable to insert the above between the VCC surface near the pin of the IC and the ground surface (see Figure 11). They are bypass capacitors to prevent bad effects from occurring to the characteristics when the power supply voltage fluctuates due to the clock, etc. It is recommended to reduce noise which overlaps the D/A output by inserting a capacitor of over 0.1F between pin 25 (AGND) and pin 26 (VSET).
HI20206
B DGND AVCC
A POWER SUPPLY
DVCC PRINTED BOARD
AGND +5V 0V
FIGURE 11.
10-11
HI20206 Typical Performance Curves
OUTPUT VOLTAGE FULL SCALE (VP-P) 0 2 OUTPUT ZERO OFFSET VOLTAGE (mV) TA = 25oC AVCC = DVCC = 5oC RL > 10k
DEVIATION RANGE 1
-10 TA = 25oC AVCC = DVCC = 5V RL > 10k
B G R
0
1 AGND (V)
2
-20
0
1.0 AGND (V)
2.0
FIGURE 12. OUTPUT VOLTAGE FULL SCALE vs VSET - AGND
FIGURE 13. OUTPUT ZERO OFFSET VOLTAGE vs VSET - AGND
OUTPUT VOLTAGE FULL SCALE (mVP-P)
0 OUTPUT ZERO OFFSET VOLTAGE (mV) VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF /3) REF = -400A AVCC = DVCC = 5V RL > 10k
1000
950
VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF /3) IREF = -400A AVCC = DVCC = 5.0V RL > 10k 0 20 40 60 80
-5
-10 -20 AMBIENT TEMPERATURE (oC)
-20
0
20
40
60
80
AMBIENT TEMPERATURE (oC)
FIGURE 14. OUTPUT VOLTAGE FULL SCALE vs AMBIENT TEMPERATURE
FIGURE 15. OUTPUT ZERO OFFSET vs AMBIENT TEMPERATURE
0 TA = 25oC VSET - AGND = 0.8V RL > 10k OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (VP-P) TA = 25oC VSET - AGND = 0.8V RL > 10k
1000
-5
950
10 4 5 POWER SUPPLY VOLTAGE (V) 6 4 5 POWER SUPPLY VOLTAGE (V) 6
FIGURE 16. OUTPUT VOLTAGE FULL SCALE vs POWER SUPPLY VOLTAGE
FIGURE 17. OUTPUT ZERO OFFSET VOLTAGE vs POWER SUPPLY VOLTAGE
10-12
HI20206 Typical Performance Curves
(Continued)
INTERNAL REFERENCE VOLTAGE (V)
1.20
INTERNAL REFERENCE VOLTAGE (V)
1.20
1.15
IREF = -400A AVCC = DVCC = 5V 0 20 40 60 80
1.15
TA = -25oC IREF = 400A 4 5 POWER SUPPLY VOLTAGE (V) 6
-20
AMBIENT TEMPERATURE (oC)
FIGURE 18. INTERNAL REFERENCE VOLTAGE vs AMBIENT TEMPERATURE
FIGURE 19. INTERNAL REFERENCE VOLTAGE vs POWER SUPPLY VOLTAGE
0
-20 CROSSTALK (dB)
-40 TA = 25oC OUTPUT VOLTAGE FULL SCALE 1VP-P fCLK = 2fDATA AVCC = DVCC = 5V RL > 10k, CL <20pF PINS 30, 32, 34 AND 36 ARE CONNECTED TO AVCC 10 DATA RATE (MHz) 20
-60
-80
-100
FIGURE 20. CROSSTALK AMONG R, G, AND B vs DATA RATE
10-13

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